Xylinx chip tools

Back in early , Xilinx first began discussing its "Extensible Processing Platform" concept, followed by a formal introduction of the Zynq product family one year later with initial sampling another year after that. Zynq wasn't the first processor-plus-programmable logic combo chip; both Xilinx and competitors like Altera had previously developed such devices. But at the time it was unique in that it embedded a full-fledged processor subsystem, including a full peripheral set, enabling the chip to operate even without a configuration bitstream loaded in the FPGA portion.

Utilizing the FPGA in the Zynq family, though, was initially a somewhat cumbersome process, not particularly amenable to software engineers. While software development targeting the ARM CPU leveraged a conventional tool flow, the FPGA design often implementing hardware-accelerated portions of the software algorithms mainly relied on conventional register-transfer-level logic design. Table 1. First, in March , came SDNet, targeting networking applications and intended as a high-level specification environment for software-defined data plane programming.

Figure 1. And now the third member of the SDx family is public Figure 2. As the flowchart shows, SDSoC enables an iterative design flow in which the developer selectively migrates portions of the application code to the FPGA, obtaining estimated latency, throughput, power consumption, and resource utilization results achieving the desired balance between software and accelerated hardware, at which point compilation finalizes both the FPGA bitmap and the software image.

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